6/25/2015HY220: Ιάκωβος Μαυροειδής1 Computer Aided Design CAD tools Functional DesignSpecificationsLogic DesignCircuit DesignPhysical DesignFabrication System Description Languages (System C) Hardware Description Languages, Schematic Editors (verilog, VHDL) Logic Synthesis Tools (Synopsys) Physical Synthesis Tools (Place & Root) Tape out and Manufacture
6/25/2015HY220: Ιάκωβος Μαυροειδής2 HW Courses HY225 Οργάνωση Υπολογιστών HY425 Αρχιτεκτονική Υπολογιστών HY534 Αρχιτ. Μεταγωγέων Πακέτων HY220 Εργαστήριο Ψηφ. Κυκλωμ. HY120 Ψηφιακή Σχεδίαση HY Αλγόριθμοι CAD εργαλείων HY422 Εισαγωγή στο VLSI Functional DesignSpecificationsLogic DesignCircuit DesignPhysical DesignFabrication
6/25/2015HY220: Ιάκωβος Μαυροειδής3 Design Verification
6/25/2015HY220: Ιάκωβος Μαυροειδής4 Consistency: same testbench at each level of abstraction Verification - Simulation Slower Simulation - Closer to reality
6/25/2015HY220: Ιάκωβος Μαυροειδής5 Testbench (verilog) Design under test (verilog) Test Vectors Generator (C, perl) Golden Model (C, perl) Test Vectors Result Vectors Same? Yes then test passed, run new No then test failed, check why… Automated Verification - Golden Model
6/25/2015HY220: Ιάκωβος Μαυροειδής6 Verification – Mixed Mode Testbench (verilog) RTL blocks (verilog) Design under test gate-level blocks (verilog) Accurate simulation/verification just for some specific blocks. No need for the whole design.
6/25/2015HY220: Ιάκωβος Μαυροειδής7 Electronic Design Automation (EDA) tools
6/25/2015HY220: Ιάκωβος Μαυροειδής8 EDA tools (cont’d)