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6/30/2015HY220: Ιάκωβος Μαυροειδής1 HY220 System Design Flow.

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Παρουσίαση με θέμα: "6/30/2015HY220: Ιάκωβος Μαυροειδής1 HY220 System Design Flow."— Μεταγράφημα παρουσίασης:

1 6/30/2015HY220: Ιάκωβος Μαυροειδής1 HY220 System Design Flow

2 6/30/2015HY220: Ιάκωβος Μαυροειδής2 Transistor : Δομική μονάδα κυκλώματος (chip)

3 6/30/2015HY220: Ιάκωβος Μαυροειδής3 Παράδειγμα: Inverter

4 6/30/2015HY220: Ιάκωβος Μαυροειδής4 Chip = γράφος transistors - Τεχνολογία Intel processor πύλες 4:1 mux 10 πύλες Η τεχνολογία (process) που χρησιμοποιούμε για την κατασκευή (fabrication) καθορίζει τις παραμέτρους των transistors και το μεγεθός του. Καθώς βελτιώνεται η τεχνολογία μικραίνει το μέγεθος του transistor (περισσότερα transistors στον ίδιο χώρο) αυξάνεται η ταχύτητα του ελαττώνεται η κατανάλωση ενέργειάς του.

5 6/30/2015HY220: Ιάκωβος Μαυροειδής5 System design flow System specification (functionality, timing) C’ description (Golden Model) Block partitioning Full Custom transistor level (Memories) HDL code (verilog) Synthesis (Standard Cells) Place and Route Chip Prototyping System Testing (functionality, timing) Hardware Implementation (next slides) Floorplanning

6 6/30/2015HY220: Ιάκωβος Μαυροειδής6 Hardware Design Methods

7 6/30/2015HY220: Ιάκωβος Μαυροειδής7 1. Full-Custom The transistor-layout is fully handmade, using a VLSI editor. Only useful for small designs due to the large expenditure. Maximal freedom High performance blocks Slow

8 6/30/2015HY220: Ιάκωβος Μαυροειδής8 2. Array-Based (Gate-Array) Large arrays of transistors are provided by the ASIC vendor. Connecting these transistors in a specific way results in the desired logic.

9 6/30/2015HY220: Ιάκωβος Μαυροειδής9 Programmable Logic Array (PLA)  PLAs have configurable “AND-plane” & “OR-plane”.  Can implement any 2-level AND-OR circuit.  Efficient physical implementation in CMOS. x0x0 x1x1 x2x2 x3x3 x4x4 x5x5 z0z0 z1z1 z2z2 z 3 = x 0 x 1 x 2 x 3 x 4 x 5 + x 0 x 1 x 2 x 5 x0x2x3x4x5x0x2x3x4x5 x0x1x2x3x4x5x0x1x2x3x4x5 x0x2x4x5x0x2x4x5 x0x1x2x5x0x1x2x5 x0x4x5x0x4x5 x1x2x3x4x1x2x3x4 configurable connection

10 6/30/2015HY220: Ιάκωβος Μαυροειδής10 Programmable Logic: LUT A mux selects which element of memory to send to output Really just a 1-bit memory

11 6/30/2015HY220: Ιάκωβος Μαυροειδής11 FPGA: Field Programmable Gate Array  CLBs can be connected to “passing” wires.  Wire segments connected by switch matrix.  Long wire segments used to connect distant CLBs.  Configuration information stored in SRAM bits that are loaded when power turns on. switch matrix wire segments configurable logic blocks (CLB) IO blocks (IOB)

12 6/30/2015HY220: Ιάκωβος Μαυροειδής12 FPGA - Routing CLB

13 6/30/2015HY220: Ιάκωβος Μαυροειδής13 What’s in a CLB (LE)? Inputs Carry out Clk LUT OutMUX Enable Carry in 1.Programmable Logic 2.Fixed Logic LE example 01

14 6/30/2015HY220: Ιάκωβος Μαυροειδής14 Programming FPGA  Lookup table implements logic functions. f(A,B,C) ABCABC  Switch matrix contains configurable clusters of pass transistors.  provides wide variety of routing options  Multiplexors and pass transistors implement routing configuration memory

15 6/30/2015HY220: Ιάκωβος Μαυροειδής15 Example: Xilinx FPGA - Wires Types of Interconnect

16 6/30/2015HY220: Ιάκωβος Μαυροειδής16 Example: Xilinx Configurable Logic Block S/R C D > ECCLR PRE LUT4 LUT3 LUT4 D > ECCLR PRE 1 1 S/R C YQ XQ Y X CLKEC G1 G2 G3 G4 F1 F2 F3 F4 H1 DIN S/R Flip Flop Main Function Generators Set/Reset Control Clock Enable Control Clock Edge Select

17 6/30/2015HY220: Ιάκωβος Μαυροειδής17 Example: Xilinx FPGA Note: CAD tools do PR, not designers Single-length lines Buffered Hex lines (1/6 blocks) Long lines and Global lines Internal 3-state Bus Direct connections

18 6/30/2015HY220: Ιάκωβος Μαυροειδής18 Block RAM (Extra RAM not using LUTs)  Most efficient memory implementation  Dedicated blocks of memory  Ideal for most memory requirements  Use multiple blocks for larger memories  Builds both single and true dual-port RAMs  CAD tool provides custom-sized block RAMs  Quickly generates optimized RAM implementation Spartan-IIE Block RAM Port A Port B

19 6/30/2015HY220: Ιάκωβος Μαυροειδής19 Example: Virtex-II Pro (Xilinx) BRAM

20 6/30/2015HY220: Ιάκωβος Μαυροειδής20 FPGA Modern Design Methodology always mumble blah always mumble blah Synthesizable Verilog Synthesis Technology Mapping LE 1 LE 2 Place and Route gates, gates, gates, … Logic Elements in FPGA Chip

21 6/30/2015HY220: Ιάκωβος Μαυροειδής21 What Do We Mean by “Synthesis”?  Logic synthesis  A program that “designs” logic from abstract descriptions of the logic  takes constraints (e.g. size, speed)  uses a library (e.g. 3-input gates)  How?  You write an “abstract” Verilog description of the logic  The synthesis tool provides alternative implementations Verilog blah blah blah or … synthesis library constraints

22 6/30/2015HY220: Ιάκωβος Μαυροειδής22 An Example  What’s cool?  You type the left, synthesis gives you the gates  It used a different library than you did. (2-input gates only)  One description suffices for a variety of alternate implementations! ... but this assumes you know a gate level implementation — that’s not an “abstract” Verilog description. a b c f module gate (f, a, b, c); output f; input a, b, c; andA (a1, a, b, c), B (a2, a, ~b, ~c), C (a3, ~a, o1); orD (o1, b, c), E (f, a1, a2, a3); endmodule module gate (f, a, b, c); output f; input a, b, c; andA (a1, a, b, c), B (a2, a, ~b, ~c), C (a3, ~a, o1); orD (o1, b, c), E (f, a1, a2, a3); endmodule

23 6/30/2015HY220: Ιάκωβος Μαυροειδής23 Automatic Logic Synthesis  Verilog synthesis may frequently interpret code differently from Verilog simulation  Unneeded Logic May Not Be Detected  Both circuits are equivalent

24 6/30/2015HY220: Ιάκωβος Μαυροειδής24 Synopsys (Synthesis and Libraries)  Synopsys tool can synthesize hardware for the components in a wide variety of libraries, as well as for complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs)  Synopsys uses a basic library with simple gates and blocks. The manufacturer adds components (standard cells) to the library.

25 6/30/2015HY220: Ιάκωβος Μαυροειδής25 Mapping and Routing  Mapping – Map logic produced by synthesis to logic elements, transforming the logic as needed  Place & Route – Place logic in a particular combinational Logic Block on an FPGA, such that the wiring delay between the block and others is acceptable  Must place critical circuit portions together to minimize wiring delays  Propagation delay of signals depends significantly on routing delay

26 6/30/2015HY220: Ιάκωβος Μαυροειδής26 Partitioning-Floorplanning Chip (abstract level) Partitioning into blocks I$ DB PP MC Floorplanning Place them in floorplanned area

27 6/30/2015HY220: Ιάκωβος Μαυροειδής27 always mumble blah always mumble blah Synthesizable Verilog Synthesis standard- cells Place and Route layout of cells gates, gates, gates, … 3. Cell-based Implementation Flow

28 6/30/2015HY220: Ιάκωβος Μαυροειδής28 Cell-based Design (or standard cells) Semi-custom: tool-based approach, where all cells corresponding to the same type use the same layout. The height of each standard cell is fixed.

29 6/30/2015HY220: Ιάκωβος Μαυροειδής29 Layout of Standard Cell The layout of a standard cell from a standard-cell library.

30 6/30/2015HY220: Ιάκωβος Μαυροειδής30 Application Specific Integrated Circuit A chip specific for a single application. Can not be reused (reprogrammed) for other purposes. Provide the layout with custom or semi-custom blocks to the manufacturer. Fabricate

31 6/30/2015HY220: Ιάκωβος Μαυροειδής31 NRE and unit cost metrics

32 6/30/2015HY220: Ιάκωβος Μαυροειδής32 ASIC VS FPGA FPGA (gate-array) Low startup cost Low financial risk Quick Manufacturing turnaround (reprogram) Easy Design Changes Can be reprogrammed Slow Clock Small on chip capacitance ASIC (full-custom+semi-custom) High cost Slow Manufacturing turnaround (~1 month) Long manufacturing time Compact design Fast clock


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