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6/23/2015HY220: Ιάκωβος Μαυροειδής1 HY220 Registers.

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Παρουσίαση με θέμα: "6/23/2015HY220: Ιάκωβος Μαυροειδής1 HY220 Registers."— Μεταγράφημα παρουσίασης:

1 6/23/2015HY220: Ιάκωβος Μαυροειδής1 HY220 Registers

2 6/23/2015HY220: Ιάκωβος Μαυροειδής2 Sequential Logic 2 storage mechanisms positive feedback charge-based

3 6/23/2015HY220: Ιάκωβος Μαυροειδής3 Naming Conventions  In our text:  a latch is level sensitive  a register is edge-triggered  There are many different naming conventions  For instance, many books call edge-triggered elements flip-flops  This leads to confusion however

4 6/23/2015HY220: Ιάκωβος Μαυροειδής4 Latch versus Register  Latch stores data when clock is low D Clk Q D Q  Register stores data when clock rises Clk D D QQ

5 6/23/2015HY220: Ιάκωβος Μαυροειδής5 Latches

6 6/23/2015HY220: Ιάκωβος Μαυροειδής6 Latch-Based Design N latch is transparent when  = 0 P latch is transparent when  = 1 N Latch Logic P Latch 

7 6/23/2015HY220: Ιάκωβος Μαυροειδής7 Timing Definitions t CLK t D t c2q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ

8 6/23/2015HY220: Ιάκωβος Μαυροειδής8 Characterizing Timing Register Latch Clk DQ t C2Q DQ t C2Q t D2Q

9 6/23/2015HY220: Ιάκωβος Μαυροειδής9 Maximum Clock Frequency t clk-Q + t p,comb + t setup = T

10 6/23/2015HY220: Ιάκωβος Μαυροειδής10 Mux-Based Positive Latches Positive latch (transparent when CLK= 1) 0 CLK 1D Q module pos_latch (clk, d, q) input clk, d; output q; reg q; or d) if (clk) q <= d; endmodule module pos_latch (clk, d, q) input clk, d; output q; reg q; or d) if (clk) q <= d; endmodule

11 6/23/2015HY220: Ιάκωβος Μαυροειδής11 Mux-Based Negative Latches1 Negative latch (transparent when CLK= 0) CLK 1 0D Q module neg_latch (clk, d, q) input clk, d; output q; reg q; or d) if (!clk) q <= d; endmodule module neg_latch (clk, d, q) input clk, d; output q; reg q; or d) if (!clk) q <= d; endmodule

12 6/23/2015HY220: Ιάκωβος Μαυροειδής12 Mux-Based Latch : Transistors NMOS onlyNon-overlapping clocks

13 6/23/2015HY220: Ιάκωβος Μαυροειδής13 Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

14 6/23/2015HY220: Ιάκωβος Μαυροειδής14 Overpowering the Feedback Loop ─ Cross-Coupled Pairs NOR-based set-reset

15 6/23/2015HY220: Ιάκωβος Μαυροειδής15 PosEdge Flip-Flop Είσοδος Ρολόι (φ) Έξοδος S R Q Q S R Q Q MASTER SLAVE module pos_reg (clk, d, q) input clk, d; output q; reg q; clk) q <= d; endmodule module pos_reg (clk, d, q) input clk, d; output q; reg q; clk) q <= d; endmodule

16 6/23/2015HY220: Ιάκωβος Μαυροειδής16 Non-Blocking Assignment ab c reg a, b, c; clk) begin b = a; c = b; end reg a, b, c; clk) begin b = a; c = b; end a b c reg a, b, c; clk) begin b <= a; c <= b; end reg a, b, c; clk) begin b <= a; c <= b; end

17 6/23/2015HY220: Ιάκωβος Μαυροειδής17 Non-Blocking Assignment ab c reg a, b, c; clk) b = a; clk) c = b; reg a, b, c; clk) b = a; clk) c = b; a b c Use non- blocking assignments for registers or ?? reg a, b, c; clk) b <= a; clk) c <= b; reg a, b, c; clk) b <= a; clk) c <= b;

18 6/23/2015HY220: Ιάκωβος Μαυροειδής18 Positive Feedback: Bi-Stability V o 1 V i 2 5 V o 1 V i 2 5 V o 1 V i1 A C B V o2 V i1 =V o2 V o1 V i2 V i2 =V o1

19 6/23/2015HY220: Ιάκωβος Μαυροειδής19 Meta-Stability Gain should be larger than 1 in the transition region

20 6/23/2015HY220: Ιάκωβος Μαυροειδής20 Metastability:Setup or Hold time violation Flip-Flop μπαίνει σε μία κατάσταση όπου το τελικό αποτέλεσμα είναι άγνωστο. Το κύκλωμα συμπεριφέρεται σαν μία αλυσίδα από inverters.

21 6/23/2015HY220: Ιάκωβος Μαυροειδής21 Pipelining Reference Pipelined

22 6/23/2015HY220: Ιάκωβος Μαυροειδής22 Example What is wrong ???

23 6/23/2015HY220: Ιάκωβος Μαυροειδής23 Example (con’t) T AND = 2ns, T OR = 1ns, T MUX = 3ns, T clk2Q = 0.5ns, T setup =0.3ns Find the critical path. Determine the clock cycle.

24 6/23/2015HY220: Ιάκωβος Μαυροειδής24 Latch-Based Pipeline


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