ΗΥ Παπαευσταθίου Γιάννης11 Correct timing depends on capacity
ΗΥ Παπαευσταθίου Γιάννης12 Asynchronous Inputs
ΗΥ Παπαευσταθίου Γιάννης13 What is Synchronisation? The action of enforcing or determining an ordering of signal events. Sampling an asynchronous signal with a clock. Sampling a synchronous signal across a clock domain. SOLUTION : A synchroniser samples a signal outside the local clock domain and outputs a version of that signal that has transitions synchronised to the local clock.
ΗΥ Παπαευσταθίου Γιάννης14 But : Metastability What happens if the input changes at exactly the time when the active edge of the clock arrives ? Output may get into a “metastable”state (intermediate Voltage) and stay in it for an undetermined duration T So do NOT use the output for a time T or do something clever !
ΗΥ Παπαευσταθίου Γιάννης15 States of buffer/inverter
ΗΥ Παπαευσταθίου Γιάννης16 Metastability
ΗΥ Παπαευσταθίου Γιάννης17 When was the signal sampled? Since a signal changes asynchronously to the sampling Clock, a sampling point could have been a little after the signal changes, yielding either 0 or 1. As a result, it does NOT matter if after the metastable period, the signal with get to 0 or to 1. All that matter is to become a valid binary value, that all of its receivers interpret in the same way !
ΗΥ Παπαευσταθίου Γιάννης18 Asynchronous bus sampling Useless ! There is no way to tell if the sampled word is a valid one(old or new) or an invalid word made by a random Selection of bits from these two words. Only possible solution : Sample the input at at least twice the frequency the signal changes so you expect to see each word at least twice ! (this is not feasible in some cases either, since you may not know the frequency the signal changes !
ΗΥ Παπαευσταθίου Γιάννης19 Another approach for busses!