6/17/2015HY220: Ιάκωβος Μαυροειδής1 HY220 Dynamic Random Access Memory
6/17/2015HY220: Ιάκωβος Μαυροειδής2 Memory Hierarchy SRAM DRAM
6/17/2015HY220: Ιάκωβος Μαυροειδής3 3 transistor DRAM cell Read Word Line Write Word Line Write Bit Line Read Bit Line Τιμή cell αποθηκεύεται στην χωρητικότητα του δυναμικού κόμβου: Refreshing λόγω ρευμάτων διαρροής (leakage) WWL RWL X X WBL RBL prechread S/A
6/17/2015HY220: Ιάκωβος Μαυροειδής4 SDRAM Memory System
6/17/2015HY220: Ιάκωβος Μαυροειδής5 SDRAM Chip Architecture
6/17/2015HY220: Ιάκωβος Μαυροειδής6 Example :Micron Double Data Rate SDRAM
6/17/2015HY220: Ιάκωβος Μαυροειδής7 Mode Register
6/17/2015HY220: Ιάκωβος Μαυροειδής8 Command Truth Table
6/17/2015HY220: Ιάκωβος Μαυροειδής9 Read Command (with auto precharge)
6/17/2015HY220: Ιάκωβος Μαυροειδής10 Read Command (without auto precharge)
6/17/2015HY220: Ιάκωβος Μαυροειδής11 Consecutive Read Bursts
6/17/2015HY220: Ιάκωβος Μαυροειδής12 Write Command (without auto precharge)
6/17/2015HY220: Ιάκωβος Μαυροειδής13 Read – Burst Stop - Write
6/17/2015HY220: Ιάκωβος Μαυροειδής14 Auto Refresh One autorefresh command every 70us : once every 7000 cycles at 100Mhz
6/17/2015HY220: Ιάκωβος Μαυροειδής15 DRAM Controller
6/17/2015HY220: Ιάκωβος Μαυροειδής16 DRAM Controller FSM