VLSI Design & Testing Center - Democritus University of Thrace 1 9 o εξάμηνο Ηλεκτρονικός Κύκλος Εργαστήριο στα FPGA.

Παρουσίαση με θέμα: "VLSI Design & Testing Center - Democritus University of Thrace 1 9 o εξάμηνο Ηλεκτρονικός Κύκλος Εργαστήριο στα FPGA."— Μεταγράφημα παρουσίασης:

1 VLSI Design & Testing Center - Democritus University of Thrace 1 9 o εξάμηνο Ηλεκτρονικός Κύκλος Εργαστήριο στα FPGA

2 VLSI Design & Testing Center - Democritus University of Thrace 2 FPGA: The chip that flip-flops

3 VLSI Design & Testing Center - Democritus University of Thrace 3 Βασικές σχεδιαστικές ιδέες  Είναι εφικτός ο σχεδιασμός?  Σχεδιαστικές προδιαγραφές  Κόστος  FPGA/CPLD ή ASIC?  Ποιόν κατασκευαστή FPGA/CPLD?  Ποια οικογένεια FPGA?  Χρόνος κατασκευής

4 VLSI Design & Testing Center - Democritus University of Thrace 4 Γιατί να χρησιμοποιούμε προγραμματιζόμενες συσκευές;  As compared to hard-wired chips, programmable chips can be customized as per needs of the user by programming  This convenience, coupled with the option of re- programming in case of problems, makes the programmable chips very attractive  Other benefits include instant turnaround, low starting cost and low risk

5 VLSI Design & Testing Center - Democritus University of Thrace 5  As compared to programmable chips, ASIC (Application Specific Integrated Circuit) has a longer design cycle and costlier ECO (Engineering Change Order)  Still, ASIC has its own market due to the added benefit of faster performance and lower cost if produced in high volume  Programmable chips are good for medium to low volume products. If you need more than 10,000 chips, go for ASIC or hard copy Γιατί να χρησιμοποιούμε προγραμματιζόμενες συσκευές;

6 VLSI Design & Testing Center - Democritus University of Thrace 6 Εισαγωγή στα FPGA  Βρισκόμαστε στην τρίτη γενιά FPGA  Απαιτείται μικρό χρονικό διάστημα για την υλοποίηση ενός κυκλώματος  Είναι η πιο διαδομένη συσκευή στα επαναπροσδιορίσιμα συστήματα  Κατάλληλο για υπολογισμούς σε επίπεδο bit

7 VLSI Design & Testing Center - Democritus University of Thrace 7 Δομή ενός FPGA

8 VLSI Design & Testing Center - Democritus University of Thrace 8 Διαφορετικοί τύποι CLB

9 VLSI Design & Testing Center - Democritus University of Thrace 9 Δομή του FPGA Διάταξη του FPGA Κουτιά Συνδέσεων

10 VLSI Design & Testing Center - Democritus University of Thrace 10 Δομικά στοιχεία του FPGA  Functional units  RAM blocks (Xilinx): implement function truth table  Multiplexers (Actel): build Boolean functions using muxes  Logic gates, flip-flops: Such as carry chains. Used for high-performance computations Address lines (input) output

11 VLSI Design & Testing Center - Democritus University of Thrace 11 Δομικά στοιχεία του FPGA  Used in connecting:  The I/O of functional units to the wires  A horizontal wire to a vertical wire  Two wire segments to form a longer wire segment

12 VLSI Design & Testing Center - Democritus University of Thrace 12 Κανάλια δρομολόγησης  Note: fixed channel widths (tracks)  Should “predict” all possible connectivity requirements when designing the FPGA chip  Channel -> track -> segment  Segment length?  Long: carry the signal longer, less “concatenation” switches, but might waste track  Short: local connections, slow for longer connections channel track segment

13 VLSI Design & Testing Center - Democritus University of Thrace 13 Δυνατές Αρχιτεκτονικές του FPGA  Τύπου νησίδας (XC3000 & XC4000)  Βασιζόμενη σε γραμμές (ACT3)  Θάλασσα από πύλες (SX Family)  Ιεραρχική  Μιας διάστασης (Garp, Chimaera)  Τύπου πλέγματος  Μερικώς διασταυρούμενη

14 VLSI Design & Testing Center - Democritus University of Thrace 14 Αρχιτεκτονική Βασικής Δομικής Μονάδας  Η αρχιτεκτονική είναι κρίσιμη για:  Την κοκκοποίηση του CLB  Την απόδοση  Τη χωρητικότητα  Την κατανάλωση ισχύος  Τα επιθυμητά χαρακτηριστικά του CLB είναι:  Χαμηλή κατανάλωση ισχύος  Μικρή καθυστέρηση  Υψηλή λειτουργικότητα  Μικρή επιφάνεια πυριτίου

15 VLSI Design & Testing Center - Democritus University of Thrace 15 Πλεονεκτήματα FPGA  Επανα-προγραμματισμός της ίδιας συσκευής  Προσομοίωση του κυκλώματος  Παραγωγή σε σύντομο χρονικό διάστημα  Σχεδιασμός του κυκλώματος σε σχηματικό διάγραμμα και HDL  Χαμηλό κόστος παραγωγής

16 VLSI Design & Testing Center - Democritus University of Thrace 16 Σχεδιαστικά Βήματα Specifications High-level Description Structural Description Behavioral VHDL, C Structural VHDL

17 VLSI Design & Testing Center - Democritus University of Thrace 17 Packaging Fabri- cation Physical Design Technology Mapping Synthesis Σχεδιαστικά Βήματα Specifications High-level Description Structural Description Placed & Routed Design X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Gate-level Design Gate-level Design Logic Description

18 VLSI Design & Testing Center - Democritus University of Thrace 18 Σχεδιαστικά Βήματα Full Custom ASIC – Standard Cell Design Standard Cell Library Design RTL-Level Design Design Methods Cost / Development Time Quality% Companies involved

19 VLSI Design & Testing Center - Democritus University of Thrace 19 Σχεδιαστικά Βήματα •Algorithmic –Encoding data, computation scheduling, balancing delays of components, etc. •Gate-level –Reduce fan-out, capacitance –Gate duplication, buffer insertion •Layout –Move transistors driven by late inputs closer to the output Effectiveness Level of detail

20 VLSI Design & Testing Center - Democritus University of Thrace 20 START UP A COMPANY, BECOME MILLIONAIRE AND RETIRE...

21 VLSI Design & Testing Center - Democritus University of Thrace 21 Σχεδιαστική ροή Detailed Design Detailed Design Ideas Design Ideas Device Programming Device Programming Timing Simulation Timing Simulation Synthesis & Implementation Synthesis & Implementation Functional Simulation Functional Simulation t pd =22.1ns f max =47.1MHz FPGA CPLD

22 VLSI Design & Testing Center - Democritus University of Thrace 22 Detailed Design •Choose the design entry method –Schematic •Gate level design •Intuitive & easy to debug –HDL (Hardware Description Language), e.g. Verilog & VHDL •Descriptive & portable •Easy to modify –Mixed HDL & schematic • Manage the design hierarchy –Design partitioning •Chip partitioning •Logic partitioning –Use vendor-supplied libraries or parameterized libraries to reduce design time –Create & manage user-created libraries (circuits)

23 VLSI Design & Testing Center - Democritus University of Thrace 23 Functional Simulation •Preparation for simulation –Generate simulation patterns •Waveform entry •HDL testbench –Generate simulation netlist • Functional simulation –To verify the functionality of your design only • Simulation results –Waveform display –Text output • Challenge –Sufficient & efficient test patterns

24 VLSI Design & Testing Center - Democritus University of Thrace 24 HDL Synthesis •Synthesis = Translation + Optimization –Translate HDL design files into gate-level netlist –Optimize according to your design constraints •Area constraints •Timing constraints •Power constraints •... • Main challenges –Learn synthesizable coding style –Write correct & synthesizable HDL design files –Specify reasonable design constraints –Use HDL synthesis tool efficiently assign z=a&b a b z

25 VLSI Design & Testing Center - Democritus University of Thrace 25 Design Implementation •Implementation flow –Netlist merging, flattening, data base building –Design rule checking –Logic optimization –Block mapping & placement –Net routing –Configuration bitstream generation • Implementation results –Design error or warnings –Device utilization –Timing reports • Challenge –How to reach high performance & high utilization implementation? FPGA CPLD a b z 01011...

26 VLSI Design & Testing Center - Democritus University of Thrace 26 Device Programming • Choose the appropriate configuration scheme –SRAM-based FPGA/CPLD devices •Downloading the bitstream via a download cable •Programming onto a non-volatile memory device & attaching it on the circuit board –OTP, EPROM, EEPROM or Flash-based FPGA/CPLD devices •Using hardware programmer •ISP • Finish the board design • Program the device • Challenge –Board design –System considerations FPGA CPLD

27 VLSI Design & Testing Center - Democritus University of Thrace 27 HDL Design Flow •Why HDL? –Can express digital systems in behavior or structure domain, shortening the design time –Can support all level of abstraction, including algorithm, RTL, gate and switch level –Both VHDL & Verilog are formal hardware description languages, thus portable • Typical HDL design flow –Use VHDL or Verilog to express digital systems •VHDL or Verilog simulation tool is required to simulate your project –Use high-level synthesis tool to obtain structural level design –Then use FPGA placement & routing tools to obtain physical FPGA netlist

28 VLSI Design & Testing Center - Democritus University of Thrace 28 Τι θα κάνουμε •Περιγραφή κυκλώματος σε VHDL •VHDL functional simulation •Έλεγχος των σημάτων εξόδου •Σύνθεση του κυκλώματος σε FPGA αρχιτεκτονική της Xilinx με το πακέτο Leonardo Spectrum (Exemplar)

29 VLSI Design & Testing Center - Democritus University of Thrace 29 Περιγραφή σε VHDL library IEEE; use IEEE.STD_LOGIC_1164.all; entity converter is port ( i3, i2, i1, i0: in STD_LOGIC; a, b, c, d, e, f, g: out STD_LOGIC); end converter; architecture case_description of converter is begin P1: process(i3, i2, i1, i0) variable tmp_in: STD_LOGIC_VECTOR(3 downto 0); begin tmp_in := i3 & i2 & i1 & i0; case tmp_in is when "0000" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1111110"); when "0001" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1100000"); when "0010" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1011011"); when "0011" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1110011"); when "0100" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1100101"); when "0101" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0110111"); when "0110" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0111111"); when "0111" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1100010"); when "1000" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1111111"); when "1001" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1110111"); when "1010" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1101111"); when "1011" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0111101"); when "1100" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0011110"); when "1101" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1111001"); when "1110" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0011111"); when "1111" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0001111"); when others => (a,b,c,d,e,f,g) <= STD_LOGIC_vector'("0000000"); end case; end process P1; end case_description;

30 VLSI Design & Testing Center - Democritus University of Thrace 30 Ακολουθίες Ελέγχου VHDL •Ανάθεση διαφόρων τιμών στις εισόδους σε διάφορες χρονικές περιόδους •Έλεγχος αν τα αποτελέσματα είναι σωστά

31 VLSI Design & Testing Center - Democritus University of Thrace 31 Έλεγχος Κυματομορφών

32 VLSI Design & Testing Center - Democritus University of Thrace 32 Προγραμματισμός του FPGA module count8(clock, clear, enable, cout); input clock, clear, enable; output [7:0] cout; reg [7:0] cout; always @(posedge clear or posedge clock) begin if (clear == 1) cout = 0; else if (enable == 1) cout = cout + 1; end endmodule...

33 VLSI Design & Testing Center - Democritus University of Thrace 33 Προγραμματισμός download cable CPLDs FPGA Programmer