ΗΥ Καλοκαιρινός Γιώργος1 Register module Reg(Q, D, Clk); // parameter N = 16; input Clk; input [N-1:0] D; output [N-1:0] Q; reg [N-1:0] Q; // Clk) Q = #`dh D; // endmodule

ΗΥ Καλοκαιρινός Γιώργος2 Register Reset_ module RegRst(Q, D, Reset_, Clk); // parameter N = 16; // input Reset_, Clk; input [N-1:0] D; output [N-1:0] Q; reg [N-1:0] Q; // Clk or negedge Reset_) begin if (!Reset_) Q = 0; else Q = #`dh D; end endmodule

ΗΥ Καλοκαιρινός Γιώργος3 Register Ld module RegLd(Q, D, Ld, Clk); // parameter N = 16; input Ld, Clk; input [N-1:0] D; output [N-1:0] Q; reg [N-1:0] Q; // Clk) if (Ld) Q = #`dh D; // endmodule

ΗΥ Καλοκαιρινός Γιώργος4 Set Clear flip-flop Strong Clear module sCff(Out, Set, Clear, Clk); // output Out; input Set, Clear, Clk; // reg Out; Clk) Out = #`dh (Out | Set) & ~Clear; // endmodule

ΗΥ Καλοκαιρινός Γιώργος5 Set Clear flip-flop Strong Set module Scff(Out, Set, Clear, Clk); // output Out; input Set, Clear, Clk; // reg Out; Clk) Out = #`dh Set | (Out & ~Clear); // endmodule

ΗΥ Καλοκαιρινός Γιώργος6 T Flip Flop module Tff(Out, Toggle, Clk); // output Out; input Toggle, Clk; // reg Out; Clk) if(Toggle) Out = #`dh ~Out; // endmodule

ΗΥ Καλοκαιρινός Γιώργος7 Positive Edge Detector module PosEdgDet(Out, In, Clk); // input In, Clk; output Out; // reg Tmp; Clk) Tmp = #`dh In; wire Out = ~Tmp & In; // endmodule

ΗΥ Καλοκαιρινός Γιώργος8 Mux2 module mux2(Out, In1, In0, Sel); // parameter N = 16; output [N-1:0] Out; input [N-1:0] In1, In0; input Sel; // wire [N-1:0] Out = Sel ? In1 : In0; // endmodule

ΗΥ Καλοκαιρινός Γιώργος9 Mux4 module mux4(Out, In3, In2, In1, In0, Sel); // parameter N = 32; input [ 1:0] Sel; input [N-1:0] In3, In2, In1, In0; output [N-1:0] Out; reg [N-1:0] Out; // or In1 or In2 or In3 or Sel) begin case ( Sel ) // synopsys infer_mux 2'b00 : Out = In0; 2'b01 : Out = In1; 2'b10 : Out = In2; 2'b11 : Out = In3; endcase end endmodule

ΗΥ Καλοκαιρινός Γιώργος10 Tris module Tris(TrisOut, TrisIn, TrisOen_); // parameter N = 32; input [N-1:0] TrisIn; input TrisOen_; output [N-1:0] TrisOut; // wire [N-1:0] TrisOut = ~TrisOen ? TrisIn : ‘bz; // endmodule

ΗΥ Καλοκαιρινός Γιώργος11 Mux4t1 RegLd Tris module MuxRegTris(Out, In0, In1, In2, In3, Select, Ld, TrisEn, Clk); // parameter N = 32; input Ld, TrisEn, Clk; input [ 1:0] Select; input [N-1:0] In0, In1, In2, In3; output [N-1:0] Out; reg [N-1:0] MuxReg; Clk) begin if(Ld) begin case(Select) 0 : MuxReg = In0; 1 : MuxReg = In1; 2 : MuxReg = In2; 3 : MuxReg = In3; endcase end wire [N-1:0] Out = TrisEn ? MuxReg : 'bz; // endmodule

ΗΥ Καλοκαιρινός Γιώργος12 Up Counter Divider module Cnt(Out, Zero, En, Clear, Clk); parameter N = 32; parameter MaxCnt = 9; input En, Clear, Clk; output Zero; output [N-1:0] Out; reg [N-1:0] Out; reg Zero; Clk) begin if(Clear) Out <= #`dh 0; else if(En) begin if(Out==MaxCnt) begin Out <= #`dh 0; Zero <= #`dh 1; end else begin Out <= #`dh Out + 1; Zero <= #`dh 0; end endmodule

ΗΥ Καλοκαιρινός Γιώργος13 Parallel to Serial Shift Register module P2Sreg(Out, In, Ld, Shift, Clk, Reset_); parameter N = 32; input Ld, Shift, Clk, Reset_; input [N-1:0] In; output Out; reg [N-1:0] TmpVal; // Clk or negedge Reset_) begin if (~Reset_) TmpVal = #`dh 0; else begin if (Ld) TmpVal = #`dh In; else if(Shift) TmpVal = #`dh TmpVal>>1; end wire Out = TmpVal[0]; endmodule

ΗΥ Καλοκαιρινός Γιώργος14 Serial to Parallel Nbit Shift Register module S2Preg(Out, In, Shift, Clear, Clk); parameter N = 32; input In, Shift, Clear, Clk; output [N-1:0] Out; reg [N-1:0] Out; // wire [N-1:0] Tmp = {Out[N-2:0],In}; Clk) begin if(Clear) Out = #`dh 0; else if(Shift) Out = #`dh Tmp; end // endmodule

ΗΥ Καλοκαιρινός Γιώργος15 Priority Enforcer and Encoder Module Priority is left <- right (MS) module PriorEnf(In, Out, OneDetected); parameter N = 8; input [N-1:0] In; output [N-1:0] Out; output OneDetected; reg [N-1:0] Out; reg OneDetected; integer i; // Temporary registers reg DetectNot; // Temporary registers begin DetectNot=1; for (i=0; i<N; i=i+1) if (In[i] & DetectNot) begin Out[i]=1; DetectNot=0; end else Out[i]=0; OneDetected= !DetectNot; end endmodule

ΗΥ Καλοκαιρινός Γιώργος16 3 to 8 Decoder Module module Dec(In, Out); input [2:0] In; output [7:0] Out; reg [7:0] Out; integer i; reg [7:0] tmp; // begin tmp = 0; for (i=0; i<8; i=i+1) if (In==i) tmp[i]=1; Out = tmp; end // endmodule

ΗΥ Καλοκαιρινός Γιώργος17 Latch module Latch(In, Out, Ld); // parameter N = 16; // input [N-1:0] In; input Ld; output [N-1:0] Out; // reg [N-1:0] Out; // or Ld) if(Ld) Out = #`dh In; // endmodule

ΗΥ Καλοκαιρινός Γιώργος18 FSM

ΗΥ Καλοκαιρινός Γιώργος19 FSM (1/5) module fsmJ(ReceiveSt, ErrorSt, Start, Stop, Error, Clk, Reset_); // input Start, Stop, Error, Clk, Reset_; output ReceiveSt, ErrorSt; // parameter [1:0] IdleState = 0, ReceiveState = 1, ErrorState = 2; // reg [1:0] FSMstate, nxtFSMstate; reg ReceiveSt, ErrorSt, nxtReceiveSt, nxtErrorSt; // or Start or Stop or Error) begin // case(FSMstate)

ΗΥ Καλοκαιρινός Γιώργος20 FSM (2/5) IdleState: begin if(Error) begin nxtFSMstate <= ErrorState; nxtReceiveSt <= 0; nxtErrorSt <= 1; end else begin if(Start) begin nxtFSMstate <= ReceiveState; nxtReceiveSt <= 1; nxtErrorSt <= 0; end else begin nxtFSMstate <= IdleState; nxtReceiveSt <= 0; nxtErrorSt <= 0; end

ΗΥ Καλοκαιρινός Γιώργος21 FSM (3/5) ReceiveState: begin if(Error) begin nxtFSMstate <= ErrorState; nxtReceiveSt <= 0; nxtErrorSt <= 1; end else begin if(Stop) begin nxtFSMstate <= IdleState; nxtReceiveSt <= 0; nxtErrorSt <= 0; end else begin nxtFSMstate <= ReceiveState; nxtReceiveSt <= 1; nxtErrorSt <= 0; end

ΗΥ Καλοκαιρινός Γιώργος22 FSM (4/5) ErrorState : begin nxtFSMstate <= IdleState; nxtReceiveSt <= 0; nxtErrorSt <= 0; end // default : begin nxtFSMstate <= IdleState; nxtReceiveSt <= 0; nxtErrorSt <= 0; end // endcase end

ΗΥ Καλοκαιρινός Γιώργος23 FSM (5/5) Clk) begin if (~Reset_) begin FSMstate <= #`dh IdleState; ReceiveSt <= #`dh 0; ErrorSt <= #`dh 0; end else begin FSMstate <= #`dh nxtFSMstate; ReceiveSt <= #`dh nxtReceiveSt; ErrorSt <= #`dh nxtErrorSt; end // endmodule

ΗΥ Καλοκαιρινός Γιώργος24 FSM (1/3) module fsmS(ReceiveSt, ErrorSt, Start, Stop, Error, Clk, Reset_); // input Start, Stop, Error, Clk, Reset_; output ReceiveSt, ErrorSt; // parameter [1:0] IdleState = 0, ReceiveState = 1, ErrorState = 2; // reg [1:0] FSMstate, nxtFSMstate; // or Start or Stop or Error) begin // case(FSMstate)

ΗΥ Καλοκαιρινός Γιώργος25 FSM (2/3) IdleState: begin if(Error) nxtFSMstate <= ErrorState; else begin if(Start) nxtFSMstate <= ReceiveState; else nxtFSMstate <= IdleState; end // ReceiveState: begin if(Error) nxtFSMstate <= ErrorState; else begin if(Stop) nxtFSMstate <= IdleState; else nxtFSMstate <= ReceiveState; end

ΗΥ Καλοκαιρινός Γιώργος26 FSM (3/3) // ErrorState : nxtFSMstate <= IdleState; // default : nxtFSMstate <= IdleState; // endcase end // Clk) begin if (~Reset_) FSMstate <= #`dh IdleState; else FSMstate <= #`dh nxtFSMstate; end // wire ReceiveSt = FSMstate[0]; wire ErrorSt = FSMstate[1]; // endmodule

ΗΥ Καλοκαιρινός Γιώργος27 FSM 1/4 module fsmM(ReceiveSt, ErrorSt, Start, Stop, Error, Clk, Reset_); // input Start, Stop, Error, Clk, Reset_; output ReceiveSt, ErrorSt; // parameter [1:0] IdleState = 0, ReceiveState = 1, ErrorState = 3; // reg [1:0] FSMstate, nxtFSMstate; // or Start or Stop or Error) begin // case(FSMstate)

ΗΥ Καλοκαιρινός Γιώργος28 FSM 2/4 IdleState: begin if(Error) nxtFSMstate <= ErrorState; else begin if(Start) nxtFSMstate <= ReceiveState; else nxtFSMstate <= IdleState; end // ReceiveState: begin if(Error) nxtFSMstate <= ErrorState; else begin if(Stop) nxtFSMstate <= IdleState; else nxtFSMstate <= ReceiveState; end

ΗΥ Καλοκαιρινός Γιώργος29 FSM 3/4 // ErrorState : nxtFSMstate <= IdleState; // default : nxtFSMstate <= IdleState; // endcase end // Clk) begin if (~Reset_) FSMstate <= #`dh IdleState; else FSMstate <= #`dh nxtFSMstate; end //

ΗΥ Καλοκαιρινός Γιώργος30 FSM 4/4 reg ReceiveSt; wire SetRcvSt = (FSMstate==IdleState)&Start; wire ClrRcvSt = (FSMstate==ReceiveState)&(Error|Stop); // Clk) begin if (~Reset_) ReceiveSt <= 0; else ReceiveSt <= (ReceiveSt | SetRcvSt)&~ClrRcvSt; end // wire ErrorSt = FSMstate[1]; // endmodule

ΗΥ Καλοκαιρινός Γιώργος31 Single Port SRAM moduleSPRAM(Addr, Data, Write_, Oen_, Cs_); // parameterADDR_WIDTH = 8, DATA_WIDTH = 8; // input Write_, Oen_, Cs_; input [ADDR_WIDTH-1:0] Addr; inout [DATA_WIDTH-1:0] Data; // reg [DATA_WIDTH-1:0] mem[(1 << ADDR_WIDTH)-1:0]; reg [DATA_WIDTH-1:0] DataTmp; // or Oen_ or Addr or Cs_ or Data) begin DataTmp = ((!Oen_ & Write_ & !Cs_) ? mem[Addr] : 'bz); if (!Write_& !Cs_) mem[Addr] = Data; end wire [DATA_WIDTH-1:0] Data = DataTmp; // endmodule

ΗΥ Καλοκαιρινός Γιώργος32 Dual Port SRAM moduleDPSRAM(WAddr, RAddr, DataIn, DataOut, Write_, Read_); // parameter ADDR_WIDTH = 8, DATA_WIDTH = 8; input Write_, Read_; input [ADDR_WIDTH-1:0] WAddr, RAddr; input [DATA_WIDTH-1:0] DataIn; output [DATA_WIDTH-1:0] DataOut; reg[DATA_WIDTH-1:0] mem[(1 << ADDR_WIDTH)-1:0]; // or DataIn or WAddr) if (!Write_) mem[WAddr] = DataIn; wire [DATA_WIDTH-1:0] DataOut = !Read_ ? mem[RAddr] : 'bz; // endmodule

ΗΥ Καλοκαιρινός Γιώργος33 Single Port SSRAM 1/2 module SPRAM(Clk, Addr, CS_, WE_, OE_, DataIn, DataOut); // parameter DATA_WIDTH = 16, ADDR_WIDTH = 16; // input [DATA_WIDTH-1:0] DataIn; input [ADDR_WIDTH-1:0] Addr; input Clk, CS_, WE_, OE_; // output [DATA_WIDTH-1:0] DataOut; // reg [DATA_WIDTH-1:0] DataInint, DataOut; reg [ADDR_WIDTH-1:0] AddrInt; reg [DATA_WIDTH-1:0] Mem[(1 << ADDR_WIDTH)-1:0]; reg CSint_, WEint_, OEint_; //

ΗΥ Καλοκαιρινός Γιώργος34 Single Port SSRAM 2/2 // Clk) begin AddrInt <= Addr; CSint_ <= CS_; WEint_ <= WE_; OEint_ <= OE_; DataInint <= DataIn; end Clk) if(~CSint_ & ~WEint_) Mem[AddrInt] = DataInint; // or CSint_ or AddrInt) DataOut = #`dh (~OEint_&~CSint_) ? Mem[AddrInt] : 'bz; // endmodule

ΗΥ Καλοκαιρινός Γιώργος35 Dual Port SSRAM 1/3 module DPRAM(Clk1, Addr1, CS1_, WE1_, OE1_, DataIn1, DataOut1, Clk2, Addr2, CS2_, WE2_, OE2_, DataIn2, DataOut2); // parameter DATA_WIDTH = 16, ADDR_WIDTH = 16; input [DATA_WIDTH-1:0] DataIn1, DataIn2; input [ADDR_WIDTH-1:0] Addr1, Addr2; input Clk1, Clk2, CS1_, CS2_, WE1_, WE2_, OE1_, OE2_; output [DATA_WIDTH-1:0] DataOut1, DataOut2; // reg [DATA_WIDTH-1:0] DataIn1int, DataOut1, DataIn2int, DataOut2; reg [ADDR_WIDTH-1:0] Addr1int, Addr2int; reg [DATA_WIDTH-1:0] Mem[(1 << ADDR_WIDTH)-1:0]; reg CS1int_, WE1int_, OE1int_, CS2int_, WE2int_, OE2int_; //

ΗΥ Καλοκαιρινός Γιώργος36 Dual Port SSRAM 2/3 // Clk1) begin Addr1int <= Addr1; CS1int_ <= CS1_; WE1int_ <= WE1_; OE1int_ <= OE1_; DataIn1int <= DataIn1; end Clk1) if(~CS1int_&~WE1int_) Mem[Addr1int] = DataIn1int; // or CS1int_ or Addr1int or Clk1) DataOut1 = #1 (~OE1int_&~CS1int_) ? Mem[Addr1int] : 'bz; //

ΗΥ Καλοκαιρινός Γιώργος37 Dual Port SSRAM 3/3 // Clk2) begin Addr2int <= Addr2; CS2int_ <= CS2_; WE2int_ <= WE2_; OE2int_ <= OE2_; DataIn2int <= DataIn2; end Clk2) if(~CS2int_&~WE2int_) Mem[Addr2int] = DataIn2; // or CS2int_ or Addr2int or Clk2) DataOut2 = #1 (~OE2int_&~CS2int_) ? Mem[Addr2int] : bz; // endmodule