ΗΥ Καλοκαιρινός Γιώργος1 PCI Bus Pin List
ΗΥ Καλοκαιρινός Γιώργος2 Initiator Target
ΗΥ Καλοκαιρινός Γιώργος3 PCI Commands Command Type C/BE[3:0]# Interrupt Acknowledge 0000 Special Cycle 0001 I/O Read 0010 I/O Write 0011 Memory Read 0110 Memory Write 0111 Configuration Read 1010 Configuration Write 1011 Memory Read Multiple 1100 Dual Address Cycle 1101 Memory Read Line 1110 Memory Write and Invalidate 1100
ΗΥ Καλοκαιρινός Γιώργος4 Basic Read Operation
ΗΥ Καλοκαιρινός Γιώργος5 Basic Write Operation
ΗΥ Καλοκαιρινός Γιώργος6 Basic Arbitration
ΗΥ Καλοκαιρινός Γιώργος7 Master Initiated Termination Completion : The master has concluded its intended transaction. Timeout : Termination when the master’s GNT#_ is deasserted and its internal Latency Timer has expired.
ΗΥ Καλοκαιρινός Γιώργος8 Master Abort Termination
ΗΥ Καλοκαιρινός Γιώργος9 Master Initiated Termination
ΗΥ Καλοκαιρινός Γιώργος10 Target Initiated Termination Retry : Termination requested before any data is tranferred. Disconnect : Termination requested with or after data was transferred on the initial phase because the target is unable to respond within the target subsequent latency requirement, and is temporarily unable continue bursting. Target Abort : Adnormal termination requested because the target detected a fatal error or the target will never be able to complete the request.
ΗΥ Καλοκαιρινός Γιώργος11 Target Initiated Termination Signaling Rules 1/2 A data phase completes on the rising edge on which IRDY# is asserted and either STOP# or TRDY# is asserted. Independent of the state of STOP#,a data transfer takes place on every rising edge of clock where both IRDY# and TRDY# are asserted. Once the target asserts STOP#, it must keep STOP# asserted until FRAME# is deasserted, whereupon it must deassert STOP#.
ΗΥ Καλοκαιρινός Γιώργος12 Target Initiated Termination Signaling Rules 2/2 Once a target has asserted TRDY# or STOP#, it cannot change DEVSEL#, TRDY# or STOP# until the current data phase completes. Whenever STOP# is asseted, the master must deassert FRAME# as soon as IRDY# can be asserted. If not already deasserted, TRDY#, STOP#, and DEVSEL# must be deasserted the clock following the completion of the last data phase and must be tri-stated the next clock.
ΗΥ Καλοκαιρινός Γιώργος13 Target Initiated Termination 1/2
ΗΥ Καλοκαιρινός Γιώργος14 Target Initiated Termination 2/2
ΗΥ Καλοκαιρινός Γιώργος15 Disconnect-1 Without Data Termination
ΗΥ Καλοκαιρινός Γιώργος16 Disconnect-2 Without Data Termination
ΗΥ Καλοκαιρινός Γιώργος17 Retry
ΗΥ Καλοκαιρινός Γιώργος18 PCI Configuration Header
ΗΥ Καλοκαιρινός Γιώργος19 Status Register Bit Assignmet
ΗΥ Καλοκαιρινός Γιώργος20 Command Register Bit Assignmet
ΗΥ Καλοκαιρινός Γιώργος21 Base Address Register Format