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Γλώσσα περιγραφής υλικού VHDL. Βασική δομή VHDL κώδικα Entity Entity (Δήλωση εισόδων – εξόδων του συστήματος) Architecture Architecture structural (περιγραφή.

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Παρουσίαση με θέμα: "Γλώσσα περιγραφής υλικού VHDL. Βασική δομή VHDL κώδικα Entity Entity (Δήλωση εισόδων – εξόδων του συστήματος) Architecture Architecture structural (περιγραφή."— Μεταγράφημα παρουσίασης:

1 Γλώσσα περιγραφής υλικού VHDL

2 Βασική δομή VHDL κώδικα Entity Entity (Δήλωση εισόδων – εξόδων του συστήματος) Architecture Architecture structural (περιγραφή δομής) rtl (περιγραφή της λειτουργίας σε επίπεδο καταχωρητή) behavioral (περιγραφή της λειτουργίας σε υψηλότερο επίπεδο)

3 Δήλωση Entity ENTITY entity_name IS PORT (port_name_1 : port_type_1; port_name_2: port _type_2; port_name_2: port _type_2; port_name_n: port_type_n); port_name_n: port_type_n); END entity_name; END entity_name;

4 Port types PORT DIRECTION PORT DIRECTION - IN -OUT-INOUT SIGNAL TYPE SIGNAL TYPE –BIT –BIT_VECTOR(WIDTH -1 DOWNTO 0) –STD_LOGIC –STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0)

5 Παράδειγμα δήλωσης Entity (1/2) ENTITY and_gate IS PORT (i1: IN BIT; i2: IN BIT; i2: IN BIT; O: OUT BIT); O: OUT BIT); END and_gate;

6 Παράδειγμα δήλωσης Entity (2/2) Library ieee; Use ieee.std_logic_1164.all; ENTITY adder IS PORT (i1: IN STD_LOGIC_VECTOR(3 DOWNTO 0); i2: IN STD_LOGIC_VECTOR(3 DOWNTO 0); i2: IN STD_LOGIC_VECTOR(3 DOWNTO 0); sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); carry: OUT STD_LOGIC); carry: OUT STD_LOGIC); END adder;

7 Δήλωση Architecture ARCHITECTURE architecture_name OF entity_name IS Δήλωση components; Δήλωση components; Δήλωση σημάτων; Δήλωση σημάτων; BEGIN BEGIN Αντιστοίχιση εισόδων component Αντιστοίχιση εισόδων component ακολουθιακές εντολές (processes) ακολουθιακές εντολές (processes) σύγχρονες εντολές σύγχρονες εντολές END [architecture_name]; END [architecture_name];

8 Δήλωση component COMPONENT component_name PORT (port_name_1 : port_type_1; PORT (port_name_1 : port_type_1; port_name_2: port _type_2; port_name_2: port _type_2; port_name_n: port_type_n); port_name_n: port_type_n); END COMPONENT; END COMPONENT;

9 Παράδειγμα δήλωσης component COMPONENT and_gate PORT (i1: IN BIT; i2: IN BIT; i2: IN BIT; O: OUT BIT); O: OUT BIT); END COMPONENT;

10 Δήλωση σήματος SIGNAL signal_name : signal_type; Παραδείγματα SIGNAL data_bus: std_logic_vector(7 downto 0); SIGNAL clock: std_logic; SIGNAL count : bit_vector(5 downto 0);

11 Αντιστοίχιση εισόδων component (ονομαστική) Label: component_name PORT MAP( port_name1 => signal_name1, PORT MAP( port_name1 => signal_name1, port_name2 => signal_name2, port_name2 => signal_name2, … port_nameN => signal_nameN); port_nameN => signal_nameN);

12 Παράδειγμα U_adder: adder PORT MAP(i1 => add1, i2 => add2, i2 => add2, sum => s, sum => s, carry => c); carry => c);

13 Αντιστοίχιση εισόδων component (με βάση τη θέση) Label: component_name PORT MAP( signal_name1, PORT MAP( signal_name1, signal_name2, signal_name2, … signal_nameN); signal_nameN);

14 Παράδειγμα U_adder: adder PORT MAP(add1, add2, add2, s, s, c); c);

15 Παράδειγμα δομικής περιγραφής

16 Τελεστές της VHDL Αριθμητικοί Αριθμητικοί +, -, *, Συνθέσιμοι /, abs, rem, mod, **Μη συνθέσιμοι Λογικοί Λογικοί AND, OR, NOT, NAND, NOR, XOR, XNOR Σχέσεων Σχέσεων =, /=,, =

17 Απόδοση τιμής σε signal signal_name <= signal_value; Παραδείγματα signal a: std_logic; signal b: std_logic_vector(6 downto 0); signal c: std_logic_vector(3 downto 0); signal d: std_logic_vector(2 downto 0); ΣωστάΛάθος a <= ‘1’;a <= “01”; b <= “ ”;b <= ‘0’; b(1) <= ‘0’; c ‘0’);c ‘0’);c <= ‘0000’; d ‘0’, others => ‘1’);d ‘0’, others => ‘1’);d <= b & c; b <= c & d;b(3 downto 1) <= d(1 downto 0); b(5 downto 3) <= d;

18 ΠΕΡΙΓΡΑΦΗ ΣΥΝΔΥΑΣΤΙΚΗΣ ΛΟΓΙΚΗΣ ENTITY gates is port (a: in bit; port (a: in bit; c: out bit); c: out bit); end gates; Architecture rtl of gates is signal b: bit; begin b <= not a; b <= not a; c <= a xor b; --c<=a xor (not a); c <= a xor b; --c<=a xor (not a); end rtl;

19 ΠΕΡΙΓΡΑΦΗ ΑΡΙΘΜΗΤΙΚΩΝ ΜΟΝΑΔΩΝ Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; ENTITY add1 is port (a, b: in std_logic; port (a, b: in std_logic; cin: in std_logic; cin: in std_logic; sum: out std_logic; sum: out std_logic; cout: out std_logic); cout: out std_logic); end add1; end add1;

20 Εντολή when Περιγραφή πολυπλέκτη Port/signal <= value1 WHEN condition1 [ELSE value2 when condition2 [ELSE value2 when condition2 …] …] ELSE valueN; ELSE valueN; ENTITY mux IS PORT (a: in std_logic; PORT (a: in std_logic; b: in std_logic; b: in std_logic; c: in std_logic; c: in std_logic; q: out std_logic); q: out std_logic); END mux; ARCHITECTURE rtl OF mux IS BEGIN q <= a when c = ‘0’ else b; q <= a when c = ‘0’ else b; END RTL;

21 Εντολή with Περιγραφή πολυπλέκτη WITH signal SELECT port/signal <= expression1 WHEN value1, port/signal <= expression1 WHEN value1, expression2 WHEN value2, expression2 WHEN value2, … expressionN WHEN OTHERS; expressionN WHEN OTHERS; ENTITY mux IS PORT (a: in std_logic; PORT (a: in std_logic; b: in std_logic; b: in std_logic; c: in std_logic; c: in std_logic; q: out std_logic); q: out std_logic); END mux; ARCHITECTURE rtl OF mux IS BEGIN WITH c SELECT q <= a WHEN ‘0’, q <= a WHEN ‘0’, b WHEN OTHERS; b WHEN OTHERS; END rtl;

22 Ακολουθιακές εντολές (1) process [process_name:] PROCESS (sensitivity list) BEGIN BEGIN Ακολουθιακές εντολές Ακολουθιακές εντολές END PROCESS [process_name];

23 COMBINATIONAL PROCESS ΠΕΡΙΓΡΑΦΗ ΣΥΝΔΥΑΣΤΙΚΗΣ ΛΟΓΙΚΗΣ PROCESS(a, b, c) BEGIN d <= (a AND b) OR c; d <= (a AND b) OR c; END PROCESS;

24 Εντολή if Περιγραφή πολυπλέκτη If condition1 then signal1 <= value1; signal1 <= value1; signal2 <= value2; signal2 <= value2; elsif condition2 then signal1 <= value3; signal1 <= value3; signal2 <= value4; signal2 <= value4; … [ELSE [ELSE signal1 <= valuen-1; signal1 <= valuen-1; signal2 <= valuen;] signal2 <= valuen;] end if; ENTITY mux IS PORT (a: in std_logic; PORT (a: in std_logic; b: in std_logic; b: in std_logic; c: in std_logic; c: in std_logic; q: out std_logic); q: out std_logic); END mux; ARCHITECTURE rtl OF mux IS BEGIN process(a, b, c) BEGIN If c = ‘0’ then q <= a; q <= a;else q <= b; q <= b; end if; end process; END rtl;

25 Εντολή CASE Περιγραφή πολυπλέκτη CASE expression IS when value1 => when value1 => signal1 <= value2; signal1 <= value2; signal2 <= value3; signal2 <= value3; when value4 => when value4 => signal1 <= value4; signal1 <= value4; signal2 <= value5; signal2 <= value5; [when others => [when others => signal1 <= valuen-1; signal1 <= valuen-1; signal2 <= valuen;] signal2 <= valuen;] end CASE; ENTITY mux IS PORT (a: in std_logic; PORT (a: in std_logic; b: in std_logic; b: in std_logic; c: in std_logic; c: in std_logic; q: out std_logic); q: out std_logic); END mux; ARCHITECTURE rtl OF mux IS BEGIN process(a, b, c) BEGIN CASE c IS WHEN ‘0’ => q <= a; q <= a; WHEN OTHERS => q <= b; q <= b; end CASE; end process; END rtl;

26 CLOCKED PROCESS (Latch με ασύγχρονο reset) PROCESS(clk, rst_n) BEGIN IF rst_n = ‘0’ THEN IF rst_n = ‘0’ THEN b ‘0’); b ‘0’); ELSIF clk= ‘1’ THEN ELSIF clk= ‘1’ THEN b <= a; b <= a; END IF; END IF; END PROCESS;

27 CLOCKED PROCESS (Latch με σύγχρονο reset) PROCESS(clk, rst_n) BEGIN IF clk = ‘1’ THEN IF clk = ‘1’ THEN if rst_n = ‘0’ then if rst_n = ‘0’ then b ‘0’); b ‘0’); else b <= a; else b <= a; end if; end if; END IF; END IF; END PROCESS;

28 CLOCKED PROCESS (Flip-flop με ασύγχρονο reset) PROCESS(clk, rst_n) BEGIN IF rst_n = ‘0’ THEN IF rst_n = ‘0’ THEN b ‘0’); b ‘0’); ELSIF clk’event and clk= ‘1’ THEN ELSIF clk’event and clk= ‘1’ THEN b <= a; b <= a; END IF; END IF; END PROCESS;

29 CLOCKED PROCESS (Flip-flop με σύγχρονο reset) PROCESS(clk, rst_n) BEGIN IF clk’event and clk= ‘1’ THEN IF clk’event and clk= ‘1’ THEN IF rst_n = ‘0’ THEN IF rst_n = ‘0’ THEN b ‘0’); b ‘0’); else b <= a; else b <= a; end if; end if; END IF; END IF; END PROCESS;

30 Εντολή for loop περιγραφή καταχωρητή ολίσθησης [label]: for identifier in range loop statements statements end loop; ENTITY shift_reg is port(clk, rst_n: in std_logic; input: in std_logic; output: out std_logic); end shift_reg; Architecture rtl of shift_reg is signal d: std_logic_vector(3 downto 0); begin process(clk, rst_n) begin if rst_n = ‘0’ then d ‘0’); elsif rising_edge(clk) then d(0) <= input; for i in 0 to 3 loop d(i+1) <= d(i); end loop; end if; end process; output <= d(3); end;

31 TESTBENCH Entity testbench_name is end testbench_name; ARCHITECTURE architecture_name of testbench_name IS Δήλωση COMPONENT Δήλωση σημάτων --signal clk: std_logic:=‘0’; BEGIN Αντιστοίχιση εισόδων/εξόδων component Ανάθεση τιμών στις εισόδους του component { clk <= not clk after 40 ns; --80 ns clock period a <= ‘1’, a <= ‘1’, ‘0’ after 50 ns, ‘0’ after 50 ns, ‘1’ after 100 ns; } ‘1’ after 100 ns; }end;

32 ΠΑΡΑΔΕΙΓΜΑ TESTBENCH Entity testbench is Entity testbench is end testbench; end testbench; Architecture test of testbench is Architecture test of testbench is component mux component mux PORT (a: in std_logic; PORT (a: in std_logic; b: in std_logic; b: in std_logic; c: in std_logic; c: in std_logic; q: out std_logic); q: out std_logic); END component; END component; signal a, b, c, q: std_logic; signal a, b, c, q: std_logic; begin U_mux: mux port map ( a =>a, b=>b, c=>c, q=> q); a <= ‘0’, a <= ‘0’, ‘1’ after 50 ns, ‘1’ after 50 ns, ‘0’ after 100 ns, ‘0’ after 100 ns, ‘1’ after 150 ns, ‘1’ after 150 ns, ‘0’ after 200 ns, ‘0’ after 200 ns, ‘1’ after 250 ns, ‘1’ after 250 ns, ‘0’ after 300 ns, ‘0’ after 300 ns, ‘1’ after 350 ns; ‘1’ after 350 ns; b <= ‘0’, b <= ‘0’, ‘1’ after 100 ns, ‘1’ after 100 ns, ‘0’ after 200 ns, ‘0’ after 200 ns, ‘1’ after 300 ns; ‘1’ after 300 ns; c <= ‘0’, c <= ‘0’, ‘1’ after 200 ns; ‘1’ after 200 ns; end test;

33 ΑΣΚΗΣΗ 1η

34 ModelSim Start -> Programs -> ModelSim Start -> Programs -> ModelSim File -> New -> Project File -> New -> Project Add Files to Project Add Files to Project Download VHDL files from Download VHDL files from directory VLSI_II_2006\ASKISI_1\


Κατέβασμα ppt "Γλώσσα περιγραφής υλικού VHDL. Βασική δομή VHDL κώδικα Entity Entity (Δήλωση εισόδων – εξόδων του συστήματος) Architecture Architecture structural (περιγραφή."

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