6/26/2015HY220: Ιάκωβος Μαυροειδής1 HY220 Asynchronous Circuits

6/26/2015HY220: Ιάκωβος Μαυροειδής2 Limits of Synchronous Systems Fully synchronous operation is not possible for very large systems because of the expense of routing a single clock and the problems of clock skew One approach is to partition the system into components that are locally clocked, “islands of synchrony surrounded by a sea of asynchrony”, also called “clock domains” These communicate using “speed independent” asynchronous protocols Each clock domain must synchronize input signals Communications Signals Clocked Subsystem Clocked Subsystem

6/26/2015HY220: Ιάκωβος Μαυροειδής3 Clock Domains  Definition of clock domain: All the logic and signals controlled by a certain clock  In other words, all events within a clock domain are synchronous to that domain’s clock Registers Clock A MM Registers Combinational Logic Clock B NN Combinational Logic Domain ADomain B

6/26/2015HY220: Ιάκωβος Μαυροειδής4 Generated or Derived Clocks  Clocks generated by a common source have related timing  Synchronous or Mesochronous  Generally treated as a single clock “domain” because setup and hold relationships can be defined DQ clock2x clock

6/26/2015HY220: Ιάκωβος Μαυροειδής5 Inter-clock domain synchronization  Synchronous signal : Signal that changes only at the positive edge or the negative edge of the clock.  Goal: Synchronize all asynchronous inputs to a clock domain.  Synchronize all signals passing from one clock domain into another using simple synchronizer DQ aClk bClk DQbSig No logic in path DQ aSig bSigSync aClk DomainbClk Domain FFA1FFB1FFB2

6/26/2015HY220: Ιάκωβος Μαυροειδής6 Asynchronous Inputs to Synchronous Systems

6/26/2015HY220: Ιάκωβος Μαυροειδής7 Synchronizer Circuit

6/26/2015HY220: Ιάκωβος Μαυροειδής8 Synchronizer Circuit

Synchronization Problems Synchronize an input from another clock domain in one FF only! Never allow asynchronous inputs to be fanned out to more than one FF within the synchronous system

6/26/2015HY220: Ιάκωβος Μαυροειδής10 Synchronization Problems  Signal generated by a faster clock synchronized by a slower clock can be missed!  It might change twice before it is sampled by the slower clock

6/26/2015HY220: Ιάκωβος Μαυροειδής11 Synchronization Problems  Signals with pulse widths long enough to assure detection have unknown width after synchronization

6/26/2015HY220: Ιάκωβος Μαυροειδής12 Synchronization Problems  Simultaneity cannot be assured during synchronization of more than one signal

6/26/2015HY220: Ιάκωβος Μαυροειδής13 Synchonizer Circuit

6/26/2015HY220: Ιάκωβος Μαυροειδής14 Synchronizer Failure & Metastability

6/26/2015HY220: Ιάκωβος Μαυροειδής15 Reliable Synchronizer Design

6/26/2015HY220: Ιάκωβος Μαυροειδής16 Elastic Buffer FIFO Elastic Buffer write clk1 F full flag Domain 1 flow control E empty flag read clk2 Domain 2 flow control clk1 clk2 Domain 1 can write data when full flag = 0 Domain 2 can read data when empty flag = 0

6/26/2015HY220: Ιάκωβος Μαυροειδής17 Purely Asynchronous Circuits

6/26/2015HY220: Ιάκωβος Μαυροειδής18 Synchronous Data Transfer

6/26/2015HY220: Ιάκωβος Μαυροειδής19 Delay Insensitive (self-timed transfer)

6/26/2015HY220: Ιάκωβος Μαυροειδής20 Delay Insensitive (self-timed transfer)

6/26/2015HY220: Ιάκωβος Μαυροειδής21 Self-timed Processing

6/26/2015HY220: Ιάκωβος Μαυροειδής22 Self-timed Processing Compositions

6/26/2015HY220: Ιάκωβος Μαυροειδής23 Self-timed Pipeline

6/26/2015HY220: Ιάκωβος Μαυροειδής24 Completion Signal Generation

6/26/2015HY220: Ιάκωβος Μαυροειδής25 Asynchronous Logic Pluses