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V ERILOG Laboratories
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ΗΥ-220 – Μαυροειδής Ιάκωβος2 Verilog Simulator > rlogin [garbis, kirkios, levantes, apraktias, pounentes, apiliotis] > source ~hy220/verilog/scripts/cds_ldv.sh > mkdir test; cd test > cp ~hy220/verilog/examples/test.v > verilog test.v > signalscan signalscan File > Open Simulation File (Διαλέξτε το test.shm/test.trn) Πατείστε το DesBrows Επιλέξτε το «test» στο Instances in Current Context Πατείστε 2 φορές στο «clk» Πατείστε το AddToWave
![ΗΥ-220 – Μαυροειδής Ιάκωβος2 Verilog Simulator > rlogin [garbis, kirkios, levantes, apraktias, pounentes, apiliotis] > source ~hy220/verilog/scripts/cds_ldv.sh > mkdir test; cd test > cp ~hy220/verilog/examples/test.v > verilog test.v > signalscan signalscan File > Open Simulation File (Διαλέξτε το test.shm/test.trn) Πατείστε το DesBrows Επιλέξτε το «test» στο Instances in Current Context Πατείστε 2 φορές στο «clk» Πατείστε το AddToWave](http://images.slideplayer.gr/16/5216690/slides/slide_2.jpg "ΗΥ-220 – Μαυροειδής Ιάκωβος2 Verilog Simulator > rlogin [garbis, kirkios, levantes, apraktias, pounentes, apiliotis] > source ~hy220/verilog/scripts/cds_ldv.sh > mkdir test; cd test > cp ~hy220/verilog/examples/test.v > verilog test.v > signalscan signalscan File > Open Simulation File (Διαλέξτε το test.shm/test.trn) Πατείστε το DesBrows Επιλέξτε το «test» στο Instances in Current Context Πατείστε 2 φορές στο «clk» Πατείστε το AddToWave")
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ΗΥ-220 – Μαυροειδής Ιάκωβος3 test.v initial begin // Start Tracing (signalscan) $shm_open("test.shm"); $shm_probe(test, "AS"); // print values of clk at stdout each time // it changes $monitor ($time, ":clk=%b", clk); #200 // Stop Tracing $shm_close(); // Stop Simulation $finish; end
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ΗΥ-220 – Μαυροειδής Ιάκωβος4 Verilog Code // // Single Seven Segment Display Driver // module DisplayS(SevenSegment, DisplaySelect, SW); // input [7:0] SW; output [3:0] DisplaySelect; output [7:0] SevenSegment; // assign DisplaySelect = ~SW[3:0]; wire [3:0] SSSel = SW[7:4]; // reg [7:0] SevenSegment; always @(SSSel) begin case (SSSel) 4'b0000 : SevenSegment = 8'h3f; 4'b0001 : SevenSegment = 8'h06; 4'b0010 : SevenSegment = 8'h5b;
![ΗΥ-220 – Μαυροειδής Ιάκωβος4 Verilog Code // // Single Seven Segment Display Driver // module DisplayS(SevenSegment, DisplaySelect, SW); // input [7:0] SW; output [3:0] DisplaySelect; output [7:0] SevenSegment; // assign DisplaySelect = ~SW[3:0]; wire [3:0] SSSel = SW[7:4]; // reg [7:0] SevenSegment; begin case (SSSel) 4 b0000 : SevenSegment = 8 h3f; 4 b0001 : SevenSegment = 8 h06; 4 b0010 : SevenSegment = 8 h5b;](http://images.slideplayer.gr/16/5216690/slides/slide_4.jpg "ΗΥ-220 – Μαυροειδής Ιάκωβος4 Verilog Code // // Single Seven Segment Display Driver // module DisplayS(SevenSegment, DisplaySelect, SW); // input [7:0] SW; output [3:0] DisplaySelect; output [7:0] SevenSegment; // assign DisplaySelect = ~SW[3:0]; wire [3:0] SSSel = SW[7:4]; // reg [7:0] SevenSegment; begin case (SSSel) 4 b0000 : SevenSegment = 8 h3f; 4 b0001 : SevenSegment = 8 h06; 4 b0010 : SevenSegment = 8 h5b;")
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ΗΥ-220 – Μαυροειδής Ιάκωβος5 4'b0111 : SevenSegment = 8'h27; 4'b1000 : SevenSegment = 8'h7f; 4'b1001 : SevenSegment = 8'h6f; 4'b1010 : SevenSegment = 8'h77; 4'b1011 : SevenSegment = 8'h7C; 4'b1100 : SevenSegment = 8'h39; 4'b1101 : SevenSegment = 8'h5E; 4'b1110 : SevenSegment = 8'h79; 4'b1111 : SevenSegment = 8'h71; endcase end // endmodule 4'b0011 : SevenSegment = 8'h4f; 4'b0100 : SevenSegment = 8'h66; 4'b0101 : SevenSegment = 8'h6d; 4'b0110 : SevenSegment = 8'h7d; Verilog Code (cont)
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ΗΥ-220 – Μαυροειδής Ιάκωβος6 module test; // reg [7:0] SW; wire [7:0] SevenSegment; wire [3:0] DisplaySelect; // DisplayS mDisplayS(SevenSegment, DisplaySelect, SW); // initial begin #10 $stop; #10 SW = 8'h01; #10 SW = 8'h11; #10 SW = 8'h21; #10 SW = 8'h31; #10 SW = 8'h41; #10 SW = 8'h51; #10 SW = 8'h61; #10 SW = 8'h71; #10 SW = 8'h81; #10 SW = 8'h91; #10 SW = 8'ha1; #10 SW = 8'hb1; #10 SW = 8'hc1; #10 SW = 8'hd1; #10 SW = 8'he1; #10 SW = 8'hf1; #100 $stop; end // endmodule Verilog Code (Test bench)
![ΗΥ-220 – Μαυροειδής Ιάκωβος6 module test; // reg [7:0] SW; wire [7:0] SevenSegment; wire [3:0] DisplaySelect; // DisplayS mDisplayS(SevenSegment, DisplaySelect, SW); // initial begin #10 $stop; #10 SW = 8 h01; #10 SW = 8 h11; #10 SW = 8 h21; #10 SW = 8 h31; #10 SW = 8 h41; #10 SW = 8 h51; #10 SW = 8 h61; #10 SW = 8 h71; #10 SW = 8 h81; #10 SW = 8 h91; #10 SW = 8 ha1; #10 SW = 8 hb1; #10 SW = 8 hc1; #10 SW = 8 hd1; #10 SW = 8 he1; #10 SW = 8 hf1; #100 $stop; end // endmodule Verilog Code (Test bench)](http://images.slideplayer.gr/16/5216690/slides/slide_6.jpg "ΗΥ-220 – Μαυροειδής Ιάκωβος6 module test; // reg [7:0] SW; wire [7:0] SevenSegment; wire [3:0] DisplaySelect; // DisplayS mDisplayS(SevenSegment, DisplaySelect, SW); // initial begin #10 $stop; #10 SW = 8 h01; #10 SW = 8 h11; #10 SW = 8 h21; #10 SW = 8 h31; #10 SW = 8 h41; #10 SW = 8 h51; #10 SW = 8 h61; #10 SW = 8 h71; #10 SW = 8 h81; #10 SW = 8 h91; #10 SW = 8 ha1; #10 SW = 8 hb1; #10 SW = 8 hc1; #10 SW = 8 hd1; #10 SW = 8 he1; #10 SW = 8 hf1; #100 $stop; end // endmodule Verilog Code (Test bench)")
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ΗΥ-220 – Μαυροειδής Ιάκωβος7 7 Segment Display
Παρόμοιες παρουσιάσεις
![ΗΥ-220 - Καλοκαιρινός Γιώργος1 Register module Reg(Q, D, Clk); // parameter N = 16; input Clk; input [N-1:0] D; output [N-1:0] Q; reg [N-1:0] Q; // always.](/16/5050425/big_thumb.jpg "ΗΥ-220 - Καλοκαιρινός Γιώργος1 Register module Reg(Q, D, Clk); // parameter N = 16; input Clk; input [N-1:0] D; output [N-1:0] Q; reg [N-1:0] Q; // always.>")
