ΗΥ220 - Βασίλης Παπαευσταθίου1 ΗΥ220 Εργαστήριο Ψηφιακών Κυκλωμάτων Χειμερινό Εξάμηνο 2007-2008 Δυναμικές Μνήμες - DRAM.

Παρουσίαση με θέμα: "ΗΥ220 - Βασίλης Παπαευσταθίου1 ΗΥ220 Εργαστήριο Ψηφιακών Κυκλωμάτων Χειμερινό Εξάμηνο 2007-2008 Δυναμικές Μνήμες - DRAM."— Μεταγράφημα παρουσίασης:

1 ΗΥ220 - Βασίλης Παπαευσταθίου1 ΗΥ220 Εργαστήριο Ψηφιακών Κυκλωμάτων Χειμερινό Εξάμηνο 2007-2008 Δυναμικές Μνήμες - DRAM

2 ΗΥ220 - Βασίλης Παπαευσταθίου2 Βασικό Block Diagram Υποσυστημάτων Μνήμης Address Decoder Word Line n Address Bits 2 n word lines m Bit Lines Memory cell RAM/ROM ονοματολογία: 32 X 8, "32 by 8" => 32 8-bit words 1M X 1, "1 meg by 1" => 1M 1-bit words

3 ΗΥ220 - Βασίλης Παπαευσταθίου3 Κελί μνήμης με 1 transistor (DRAM) Εγγραφή - Write: 1.Οδηγούμε την bit line 2.Επιλέγουμε γραμμή (row select) Ανάγνωση - Read: 1.Προφορτίζουμε (precharge) την bit line σε Vdd/2 2.Επιλέγουμε γραμμή (row select) 3.Το κελί και η bit line μοιράζονται τα φορτία (charge sharing) 4.Sense στην bit line (sense amplifier) Μπορεί να ανιχνεύει πολύ μικρές αλλαγές 5.Write: επαναφέρουμε την τιμή Ανανέωση – Refresh : –Αρκεί ένα απλό read σε κάθε κελί row select bit

4 ΗΥ220 - Βασίλης Παπαευσταθίου4 Κλασσική Οργάνωση DRAM (τετραγωνική) rowdecoderrowdecoder row address Column Selector & I/O Circuits Column Address data RAM Cell Array word (row) select bit (data) lines Row and Column Address together select 1 bit a time Each intersection represents a 1-T DRAM Cell Square keeps the wires short: Power and speed advantages Less RC, faster precharge and discharge is faster access time!

5 ΗΥ220 - Βασίλης Παπαευσταθίου5 Λογική Οργάνωση DRAM (4 Mbit) Square root of bits per RAS/CAS –Row selects 1 row of 2048 bits from 2048 rows –Col selects 1 bit out of 2048 bits in such a row Column Decoder SenseAmps & I/O MemoryArray (2,048 x 2,048) A0…A10 … 11 Word Line Storage Cell ROWDECODERROWDECODER 11 4 Mbit = 22 address bits 11 row address bits 11 col address bits

6 ΗΥ220 - Βασίλης Παπαευσταθίου6 Σήματα ελέγχου (RAS_L, CAS_L, WE_L, OE_L) όλα active low Κοινό bus δεδομένων D - εισόδου κα ι εξόδου (Din & Dout): –WE_L ενεργοποιείται (Low), OE_L απενεργοποιείται (High) D χρησιμοποιέιται σαν είσοδος στην DRAM –WE_L απενεργοποιείται (High), OE_L ενεργοποιείται (Low) D χρησιμοποιέιται σαν έξοδος από την DRAM Οι διευθύνσεις γραμμής και στήλης μοιράζονται τα ίδια pins (A) –RAS_L ενεργοποιείται (low) -> A αποθηκεύεται σαν row address –CAS_L ενεργοποιείται (low) -> A αποθηκεύεται σαν column address –RAS/CAS edge-sensitive A D OE_L 256K x 8 DRAM 98 WE_LCAS_LRAS_L Τα σήματα της DRAM

7 ΗΥ220 - Βασίλης Παπαευσταθίου7 Απλοποιημένο διάγραμμα χρονισμού DRAM Η διεύθυνση δίνεται σε 2 βήματα ReadWrite

8 ΗΥ220 - Βασίλης Παπαευσταθίου8 OE_L ARow Address WE_L Junk Read Access Time Output Enable Delay CAS_L RAS_L Col AddressRow AddressJunkCol Address DHigh ZData Out DRAM Read Cycle Time Early Read Cycle: OE_L asserted before CAS_L Late Read Cycle: OE_L asserted after CAS_L Κάθε προσπέλαση DRAM ξεκινάει με: –Ενεργοποίηση του RAS_L –2 τρόποι ανάγνωση: early or late JunkData OutHigh Z Τυπικός χρονισμός Ανάγνωσης DRAM A D OE_L 256K x 8 DRAM 98 WE_LCAS_LRAS_L Setup Hold

9 ΗΥ220 - Βασίλης Παπαευσταθίου9 Τα βήματα για Early Read Assert Row Address Assert RAS_L –Start read cycle –Meet Row Addr setup time before RAS/hold time after RAS Assert OE_L Assert Col Address Assert CAS_L –Meet Col Addr setup time before CAS/hold time after CAS Valid Data Out after access time Disassert OE_L, CAS_L, RAS_L to end cycle

10 ΗΥ220 - Βασίλης Παπαευσταθίου10 Assert Row Address Assert RAS_L –Start read cycle –Meet Row Addr setup time before RAS/hold time after RAS Assert Col Address Assert CAS_L –Meet Col Addr setup time before CAS/hold time after CAS Assert OE_L Valid Data Out after access time Disassert OE_L, CAS_L, RAS_L to end cycle Τα βήματα για Late Read

11 ΗΥ220 - Βασίλης Παπαευσταθίου11 WE_L ARow Address OE_L Junk WR Access Time CAS_L RAS_L Col AddressRow AddressJunkCol Address DJunk Data In Junk DRAM WR Cycle Time Early Wr Cycle: WE_L asserted before CAS_LLate Wr Cycle: WE_L asserted after CAS_L Τυπικός χρονισμός Εγγραφής DRAM Κάθε προσπέλαση DRAM ξεκινάει με: –Ενεργοποίηση του RAS_L –2 τρόποι εγγραφής: early or late A D OE_L 256K x 8 DRAM 98 WE_LCAS_LRAS_L Setup Hold

12 ΗΥ220 - Βασίλης Παπαευσταθίου12 Key DRAM Timing Parameters t RAC : minimum time from RAS line falling to the valid data output. –Quoted as the speed of a DRAM –A fast 4Mb DRAM t RAC = 60 ns t RC : minimum time from the start of one row access to the start of the next. –t RC = 110 ns for a 4Mbit DRAM with a t RAC of 60 ns t CAC : minimum time from CAS line falling to valid data output. –15 ns for a 4Mbit DRAM with a t RAC of 60 ns t PC : minimum time from the start of one column access to the start of the next. –35 ns for a 4Mbit DRAM with a t RAC of 60 ns

13 ΗΥ220 - Βασίλης Παπαευσταθίου13 Memory in Desktop Computer Systems: SRAM (lower density, higher speed) used in CPU register file, on- and off-chip caches. DRAM (higher density, lower speed) used in main memory Closing the GAP: 1.Caches are growing in size. 2.Innovation targeted towards higher bandwidth for memory systems: –SDRAM - synchronous DRAM –RDRAM - Rambus DRAM –EDORAM - extended data out SRAM –multibank DRAM

14 ΗΥ220 - Βασίλης Παπαευσταθίου14 DRAM with Column buffer Column Latches SenseAmps MemoryArray (2,048 x 2,048) A0…A10 … Word Line Storage Cell ROWDECODERROWDECODER 11 MUX Pull column into fast buffer storage Access sequence of bit from there

15 ΗΥ220 - Βασίλης Παπαευσταθίου15 Optimized Access to Cols in Row Often want to access a sequence of bits Page mode –After RAS / CAS, can access additional bits in the row by changing column address and strobing CAS Static Column mode –Change column address (without repeated CAS) to get different bit Nibble mode –Pulsing CAS gives next bit mod 4 Video ram –Serial access

16 ΗΥ220 - Βασίλης Παπαευσταθίου16 More recent DRAM enhancements EDO - extended data out (similar to fast-page mode) –RAS cycle fetched rows of data from cell array blocks (long access time, around 100ns) –Subsequent CAS cycles quickly access data from row buffers if within an address page (page is around 256 Bytes) SDRAM - synchronous DRAM –clocked interface –uses dual banks internally. Start access in one bank then next, then receive data from first then second. DDR - Double data rate SDRAM –Uses both rising (positive edge) and falling (negative) edge of clock for data transfer. (typical 100MHz clock with 200 MHz transfer). RDRAM - Rambus DRAM –Entire data blocks are access and transferred out on a high-speed bus- like interface (500 MB/s, 1.6 GB/s) –Tricky system level design. More expensive memory chips.

17 ΗΥ220 - Βασίλης Παπαευσταθίου17 256 Mbit SDRAM Addressing

18 ΗΥ220 - Βασίλης Παπαευσταθίου18 Functional Block Diagram 8 Meg x 16 SDRAM

19 ΗΥ220 - Βασίλης Παπαευσταθίου19 SDRAM Details Multiple “banks” of cell arrays are used to reduce access time: –Each bank is 4K rows by 512 “columns” by 16 bits (for our part) Read and Write operations as split into RAS (row access) followed by CAS (column access) These operations are controlled by sending commands –Commands are sent using the RAS, CAS, CS, & WE pins. Address pins are “time multiplexed” –During RAS operation, address lines select the bank and row –During CAS operation, address lines select the column. “ ACTIVE ” command “opens” a row for operation –transfers the contents of the entire to a row buffer Subsequent “ READ ” or “ WRITE ” commands modify the contents of the row buffer. For burst reads and writes during “ READ ” or “ WRITE ” the starting address of the block is supplied. –Burst length is programmable as 1, 2, 4, 8 or a “full page” (entire row) with a burst terminate option. Special commands are used for initialization (burst options etc.) A burst operation takes  4 + n cycles (for n words)

20 ΗΥ220 - Βασίλης Παπαευσταθίου20 Mode Register

21 ΗΥ220 - Βασίλης Παπαευσταθίου21 Command Truth Table

22 ΗΥ220 - Βασίλης Παπαευσταθίου22 Βασικές Χρονικές Παράμετροι SDRAM t RCD : ACTIVE to READ or WRITE delay CL : CAS Latency t RAS : ACTIVE to PRECHARGE time t RP : PRECHARGE Period t WR : WRITE recovery time t RC : ACTIVE to ACTIVE time

23 ΗΥ220 - Βασίλης Παπαευσταθίου23 READ burst (with auto precharge)

24 ΗΥ220 - Βασίλης Παπαευσταθίου24 WRITE burst (with auto precharge)

25 ΗΥ220 - Βασίλης Παπαευσταθίου25 DDR Read Command (with auto precharge)

26 ΗΥ220 - Βασίλης Παπαευσταθίου26 DDR Read Command (without auto precharge)

27 ΗΥ220 - Βασίλης Παπαευσταθίου27 DDR: Consecutive Read Bursts

28 ΗΥ220 - Βασίλης Παπαευσταθίου28 DDR Write Command (without auto precharge)

29 ΗΥ220 - Βασίλης Παπαευσταθίου29 DDR: Read – Burst Stop - Write

30 ΗΥ220 - Βασίλης Παπαευσταθίου30 Auto Refresh One autorefresh command every 70us : once every 7000 cycles at 100Mhz

31 ΗΥ220 - Βασίλης Παπαευσταθίου31 Volatile Memory Comparison SRAM Cell Larger cell  lower density, higher cost/bit No dissipation Read non-destructive No refresh required Simple read  faster access Standard IC process  natural for integration with logic DRAM Cell Smaller cell  higher density, lower cost/bit Needs periodic refresh, and refresh after read Complex read  longer access time Special IC process  difficult to integrate with logic circuits Density impacts addressing word line bit line word line bit line The primary difference between different memory types is the bit cell. addr data

32 ΗΥ220 - Βασίλης Παπαευσταθίου32 SDRAM Recap General Characteristics –Optimized for high density and therefore low cost/bit –Special fabrication process – DRAM rarely merged with logic circuits. –Needs periodic refresh (in most applications) –Relatively slow because: High capacity leads to large cell arrays with high word- and bit- line capacitance Complex read/write cycle. Read needs “precharge” and write- back word line bit line –Multiple clock cycles per read or write access –Multiple reads and writes are often grouped together to amortize overhead. Referred to as “bursting”. DRAM bit cell