HY220: Ιάκωβος Μαυροειδής System Design Flow 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Transistor : Δομική μονάδα κυκλώματος (chip) 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής Παράδειγμα: Inverter 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής Chip = γράφος transistors - Τεχνολογία 4:1 mux 10 πύλες Intel processor 10 000 000 πύλες Η τεχνολογία (process) που χρησιμοποιούμε για την κατασκευή (fabrication) καθορίζει τις παραμέτρους των transistors και το μεγεθός του. Καθώς βελτιώνεται η τεχνολογία μικραίνει το μέγεθος του transistor (περισσότερα transistors στον ίδιο χώρο) αυξάνεται η ταχύτητα του ελαττώνεται η κατανάλωση ενέργειάς του. 4/17/2017 HY220: Ιάκωβος Μαυροειδής

System design flow Hardware Implementation (next slides) System specification (functionality, timing) C’ description (Golden Model) Block partitioning HDL code (verilog) Full Custom transistor level (Memories) Synthesis (Standard Cells) Hardware Implementation (next slides) Floorplanning Place and Route System Testing (functionality, timing) Chip Prototyping 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Hardware Design Methods 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής 1. Full-Custom The transistor-layout is fully handmade, using a VLSI editor. Only useful for small designs due to the large expenditure. Maximal freedom High performance blocks Slow 4/17/2017 HY220: Ιάκωβος Μαυροειδής

2. Array-Based (Gate-Array) Large arrays of transistors are provided by the ASIC vendor. Connecting these transistors in a specific way results in the desired logic. 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Programmable Logic Array (PLA) configurable connection x0x2x3x4x5 x0x1x2x3x4x5 x0x2x4x5 x0x1x2x5 x0x4x5 x1x2x3x4 configurable connection x0 x1 x2 x3 x4 x5 z0 z1 z2 z3 = x0x1x2x3x4x5 + x0x1x2x5 PLAs have configurable “AND-plane” & “OR-plane”. Can implement any 2-level AND-OR circuit. Efficient physical implementation in CMOS. 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Programmable Logic: LUT A mux selects which element of memory to send to output Really just a 1-bit memory 4/17/2017 HY220: Ιάκωβος Μαυροειδής

FPGA: Field Programmable Gate Array switch matrix wire segments configurable logic blocks (CLB) IO blocks (IOB) CLBs can be connected to “passing” wires. Wire segments connected by switch matrix. Long wire segments used to connect distant CLBs. Configuration information stored in SRAM bits that are loaded when power turns on. 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής FPGA - Routing CLB 1 CLB 00 1 CLB CLB 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής What’s in a CLB (LE)? Carry out Programmable Logic Fixed Logic MUX Out Inputs LUT Clk 1 Enable Carry in LE example 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής Programming FPGA Lookup table implements logic functions. f(A,B,C) 1 0 1 2 3 4 5 6 7 A B C 0 1 2 3 1 1 configuration memory Multiplexors and pass transistors implement routing. Switch matrix contains configurable clusters of pass transistors. provides wide variety of routing options 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Example: Xilinx FPGA - Wires Types of Interconnect 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Example: Xilinx Configurable Logic Block Clock Edge Select Main Function Generators S/R C D > EC CLR PRE LUT4 LUT3 1 YQ XQ Y X CLK G1 G2 G3 G4 F1 F2 F3 F4 H1 DIN S/R Set/Reset Control Clock Enable Control Flip Flop 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής Example: Xilinx FPGA Note: CAD tools do PR, not designers Direct connections Internal 3-state Bus Long lines and Global lines Buffered Hex lines (1/6 blocks) Single-length lines 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής Block RAM (Extra RAM not using LUTs) Port A Spartan-IIE Block RAM Port B Most efficient memory implementation Dedicated blocks of memory Ideal for most memory requirements Use multiple blocks for larger memories Builds both single and true dual-port RAMs CAD tool provides custom-sized block RAMs Quickly generates optimized RAM implementation 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής Example: Virtex-II Pro (Xilinx) BRAM 4/17/2017 HY220: Ιάκωβος Μαυροειδής

FPGA Modern Design Methodology always mumble blah Synthesis gates, gates, gates, … Technology Mapping Synthesizable Verilog Place and Route LE 1 LE 2 Logic Elements in FPGA Chip 4/17/2017 HY220: Ιάκωβος Μαυροειδής

What Do We Mean by “Synthesis”? Logic synthesis A program that “designs” logic from abstract descriptions of the logic takes constraints (e.g. size, speed) uses a library (e.g. 3-input gates) How? You write an “abstract” Verilog description of the logic The synthesis tool provides alternative implementations constraints Verilog blah blah blah synthesis or … library 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής An Example What’s cool? You type the left, synthesis gives you the gates It used a different library than you did. (2-input gates only) One description suffices for a variety of alternate implementations! ... but this assumes you know a gate level implementation — that’s not an “abstract” Verilog description. module gate (f, a, b, c); output f; input a, b, c; and A (a1, a, b, c), B (a2, a, ~b, ~c), C (a3, ~a, o1); or D (o1, b, c), E (f, a1, a2, a3); endmodule a b c f 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Automatic Logic Synthesis Verilog synthesis may frequently interpret code differently from Verilog simulation Unneeded Logic May Not Be Detected Both circuits are equivalent 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Synopsys (Synthesis and Libraries) Synopsys tool can synthesize hardware for the components in a wide variety of libraries, as well as for complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs) Synopsys uses a basic library with simple gates and blocks. The manufacturer adds components (standard cells) to the library. 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής Mapping and Routing Mapping – Map logic produced by synthesis to logic elements, transforming the logic as needed Place & Route – Place logic in a particular combinational Logic Block on an FPGA, such that the wiring delay between the block and others is acceptable Must place critical circuit portions together to minimize wiring delays Propagation delay of signals depends significantly on routing delay 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Partitioning-Floorplanning Chip (abstract level) Partitioning into blocks MC I$ DB PP Place them in floorplanned area 4/17/2017 HY220: Ιάκωβος Μαυροειδής

3. Cell-based Implementation Flow always mumble blah Synthesizable Verilog Synthesis standard- cells Place and Route layout of cells gates, gates, gates, … 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Cell-based Design (or standard cells) Semi-custom: tool-based approach, where all cells corresponding to the same type use the same layout. The height of each standard cell is fixed. 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Layout of Standard Cell The layout of a standard cell from a standard-cell library. 4/17/2017 HY220: Ιάκωβος Μαυροειδής

Application Specific Integrated Circuit A chip specific for a single application. Can not be reused (reprogrammed) for other purposes. Fabricate Provide the layout with custom or semi-custom blocks to the manufacturer. 4/17/2017 HY220: Ιάκωβος Μαυροειδής

NRE and unit cost metrics 4/17/2017 HY220: Ιάκωβος Μαυροειδής

HY220: Ιάκωβος Μαυροειδής ASIC VS FPGA FPGA (gate-array) Low startup cost Low financial risk Quick Manufacturing turnaround (reprogram) Easy Design Changes Can be reprogrammed Slow Clock Small on chip capacitance ASIC (full-custom+semi-custom) High cost Slow Manufacturing turnaround (~1 month) Long manufacturing time Compact design Fast clock 4/17/2017 HY220: Ιάκωβος Μαυροειδής