7/15/2015HY220: Ιάκωβος Μαυροειδής2 Assign 1 CL1CL2 7ns 6.7ns 0.1 ns 0.7 ns5 ns T c-q = 0.2ns, T setup = 0.1ns, T jitter = 0.1ns, Clock period = ??
7/15/2015HY220: Ιάκωβος Μαυροειδής3 Assign 1 : Solution CL1CL2 7ns 6.7ns 0.1 ns 0.7 ns5 ns T c-q = 0.2ns, T setup = 0.1ns, T jitter = 0.1ns, T >= T c-q + T CL + T setup - δ + 2 T jitter T 1 >= 0.2 + 7 + 0.1 + 0.1 + 2 * 0.1 = 7.6 ns T 2 >= 0.2 + 6.7 + 0.1 + 0.7 + 2 * 0.1 = 7.9 ns T >= 7.9ns
7/15/2015HY220: Ιάκωβος Μαυροειδής4 Assign 2 Bus Specifications Synchronous Bus Split Transactions between masters Read : Cmd to Data delay = 2 clock cycles Write : Cmd + Data at the same cycle Masters on Bus Master1 : 1 read / 5clock cycles. Master2 : writes in full throughput. Find maximum throughput of Master 2 when we have. 1.Daisy Chain arbiter 2.Centralized Round Robin Arbiter. Serves concurrent requests from 2 Masters in RR fashion.
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